VOYAGER

Voyager LECP Data Analysis Handbook

 

Calibrations and Channel Definitions

 

The Voyager (MJS) LECP Pulse Height Analyzer (PHA)

 

Circuit Detail (continued)

 

A/D Conversion. Most of the converter circuitry is on the 1552 (Fast Comparator and Multiplex) and 1540 (A/D Converter Logic) boards with an additional two binaries on the 1530 board. These circuits are the Cycled Power section of the "PHA-1 Detail" in Figure 2. Multiplexing of signals will be discussed separately. The input to the A/D converter is defined as the output of the hybrid inverter amplifier (EME 0269) U4 of 1530 which is -8.0 V full scale in all cases.

 

A/D conversion is accomplished in successive approximation using a Micro Networks Corporation MN-121 12 bit R-2R ladder network. R is 50 K ohms which is compatible with the CMOS drive circuitry and minimizes current drain. Only 10 bits are used; the device is overspecified to improve the long term stability. The ladder is a thin film nickel chromium array of 12 bit accuracy over the standard military thermal environment. The absolute accuracy of the resistors is only 10%; however, the comparison resistor is included in the array providing the required .05% matching accuracy with a relative temperature coefficient (tracking between resistors) of about 1 ppm/ºC.

 

An 8.000 volt reference circuit is designed around an EME-0270 hybrid and a 1N4568A 6.4 V precision zener. The amplifier is designed to turn ON and settle to within 1 mV of final value in less than 10 microseconds. This saves considerable standby power. An absolute accuracy of 2 millivolts or better was desired to minimize package calibration and allow board interchangeability. Another hybrid, the EME-0266, is used for feedback trim and establishing the reference level. This is somewhat similar to the Micro Networks package in that the absolute resistance is not very accurate but the temperature tracking is excellent. Resistance is specified as 20% or better with the ratio of taps maintained to better than .05%. Careful layout produced an excellent thin-film array, one of the few produced to have a 100% yield over the full thermal environment. Thus, the reference level is adjusted to within 2 mV after the 1530 board is completed by jumpering the necessary taps of the 0266. The 1N4568A reference zener is specified as less than 10 mV shift over the full military range with a T.C. of .001%/ºC. This drift can be halved by going to a 1N4569A at a significant increase in cost. For a ±50ºC environment, the drift contribution is equal to that of the feedback divider.

 

Figure 4 shows a block diagram of the analog portion in the A/D converter. Total error will be discussed under "Multiplexers" (following; scroll down).  Amplifier analysis is available in the memo EME-75-201, 19 August, 1975, "Hybrid Level Qualification of the EME-0270 Positive Output Op Amp" (archived at the Applied Physics Laboratory). The 10 bit system has the LSB @ 8.000/1024 or about 8 mV. The flight boards were individually tested thermally, producing the following results of reference voltage stability.

 

8V REFERENCE VOLTAGE FOR THE LECP PHA

 

			-50ºC	ROOM	+50ºC
Prototype	1 Sept. 76	PHA-1	7.992 V	8.000V	7.999V
		PHA-2	7.988	7.998	7.998
Flight 1	16 Nov. 76	PHA-1	7.990	7.999	8.005
		PHA-2	7.996	7.997	8.000
Flight 2	20 Dec. 76	PHA-1	7.996	7.996	8.000
		PHA-2	7.989	7.998	8.005

 

The above measurement included all sources of temperature dependence, the zener, amplifier offset, and precision divider. Note the lower temperature is considerably colder than the expected operating limit of the experiment.

 

Reference shift with input voltage is also of interest. The +12 V "S" line is probably the most significant. For the same units the following measurements were made.

 

8V REFERENCE OUTPUT FOR ±10% INPUT POWER (ALL LINES)

 

		-50ºC		ROOM		+50ºC
		-10%	+10%	-10%	+10%	-10%	+10%
Proto	(1)	7.991	7.995	7.998	8.002	7.997	8.000
	(2)	7.987	7.989	7.997	8.000	7.996	7.999
Flt. 1	(1)	7.987	7.992	7.997	8.004	8.004	8.009
	(2)	7.995	7.997	7.997	8.001	8.001	8.003
Flt. 2	(1)	7.995	7.997	7.996	7.998	7.998	8.001
	(2)	7.988	7.991	7.997	NA	8.002	8.006

 

The above shows the reference accuracy is sufficient for a 10 bit absolute measurement at any one temperature with a one bit uncertainty over the thermal range. In conjunction with other error sources this suggests the use of individual calibration for each PHA over the environment. However, in the LECP the PHA thermal shifts are small with respect to the signal processing chain, especially the logarithmic amplifiers, and overall calibration is a better method of maintaining total available accuracy.

 

The comparator circuit is designed around discrete components and included in the schematic of the 1520 board. The configuration is similar to that of the hybrid amplifiers with an input JFET matched pair driving a PNP current mirror to produce very high input stage gain. For positive input voltages the left hand JFET is more conductive, thus driving pin 7 of Q1 into saturation, clamping the following PNP OFF with a resulting high output at the "HI/LO" output. As the voltage drops below zero the unbalance in current drives Q3 causing a voltage increase at pin 14 of the CA3045 NPN transistor array. Pin 5 begins to drop in voltage. Positive feedback to the R32-R37 divider drives the pin 11 current reference and about 2 millivolts of hysteresis is produced. C5 is used to maintain a controlled output time constant of about 0.4 microsecond. The comparator could be fabricated as a hybrid; it is not from a cost savings view as only one per A/D section is required.

 

The case of U4 is grounded to minimize noise pickup. The input Z at pin 7 is 50 kohms and susceptible to strays coupled through the case itself. Stability of measurements improved noticeably after the case was grounded with last bit uncertainty approximating statistical randomness when the voltage is near the transition point for the next bit.

 

U5, a five transistor array from RCA, provides not only the high-speed NPN units for the comparator, but clamping at the input (Pin 7 of Q4). The diode is the substrate to collector diode of the adjacent transistor, thus obtaining both positive and negative clamp of the input signal with no additional components. The diode wired NPN across the collectors of Q1 prevents the voltage on Q4-2 from dropping more than about 1.2 V below the positive bus, thereby maintaining speed in the comparator by holding the 2N5564 in the pentode region and preventing Q3 from saturating. R39 isolates the comparator from its load and protects the output stage.

 

The comparator is tailored identically to the hybrid operational amplifiers, and additional DC current is added to the PNP mirror (with the appropriate phase) to trim the balance point to less than about 1 mV. This is done dynamically in the flight boards. The U4 hybrid amplifier is trimmed statistically for less than 1 mV output error with pin 1 and 12 of U1 shorted to ground and the tester setup for LEMPA operation (i.e., the U1 multiplexer is connected with U2 and U3 clamped at the #1 or zero volt input terminal as will be discussed later). The tester is then set up to CAL LEMPA and allowed to run. The comparator is trimmed to the middle of the resistance range that holds a channel 1 readout of 0002.

 

Note the trim voltage is marked as +12F. This is capacitively coupled to the +12 V input by 1 ufd (C14) of the 1530 board. This reduces the power line noise coupling of the trim resistor, otherwise all noise components will drive the PNPs (Q1) directly against the trimmer. The same technique is used with U4. The coupling rolls off below about 17 Hz. A better arrangement for future designs is to put the bias AC coupling directly at the emitters of Q1 and R42.

 

The U4 hybrid amplifier is used to scale the input level and invert it. The scaling resistors are in series with the three multiplexers and set the gain in reference to the 120 kohm 1/4% feedback resistors of U4. The negative output is needed for comparison with the positive drive from the U6 R/2R ladder network. The ladder is driven from COS-MOS hex buffers powered from the 8.000 V reference supply. Thus when the total current contribution from the ladder binary segments equals the current from the inverting amplifier U4 (as determined by the U6 internal summing resistor between pins 15 and 16) a null balance occurs. A successive approximation technique is used wherein the most significant bit is originally set to unity (with the remainder to zero volts) and each successive bit energized. The circuitry keeps each bit high if the comparator detects a negative input (i.e., not enough voltage) and resets it to zero if the comparator detects a positive level (too much voltage).

 

A/D Conversion Timing Cycle

 

0.	At the initiation of a GO signal, the A/D power is turned ON and the first measurement is maintained in the MSB HI state for 4 to 5 clock periods (80 to 100 microseconds) while power transients normalize. Control circuits are shown on the ID 1540 schematic. The Data Clock is running and U9 (1 of 10 counter) is stepping.
1.	U9 of ID 1540 reaches the "3" output (pin 7) which sets U2 pin 13 HI and clocks U2 pin 3.   The second bit is high and the MSB is clocked HI or LO depending on the state of the comparator.  A delay of about 44 OnSec is introduced in the clock to the MSB to insure sufficient time for the previous set to clear (this is not really necessary for the MSB since that input does not remain high during the first three steps of the 1 of 10).
2.	The sequence continues until U9 has completed all 10 steps and is back with the 0 output (pin 3) just transitioned to HI. This clocks the ENABLE binary U10-1 to the Q2 LO so that at the next cycle it clocks the U11 1 of 10 counter and causes it to step to the 1 output.
3.	The sequence continues until U11 steps to the 2 output (pin 4).  This sets D of the Reset binary HI so that at the next clock positive transition U10-13 goes HI causing a reset pulse.  Both steppers are reset to 0 and the Enable binary again selects U9.
4.	Three clock intervals are required until U9 again reaches the 3 output and the next most significant bit is set.  This extra duration allows the multiplexer and inverting amplifier time to settle as the new analog channel is selected.  Note the Reset pulse caused a Clamp pulse which also clocks the master A, B and C timing flip-flops advancing them to the second state.
5.	The sequence continues to cycle until four multiplex channels have been converted and the fourth clamp pulse causes conversion power shut off as previously described until "Conversion Cycle Timing."

 

Note that the number of buffers driving the R/2R ladder are variable. The first two most significant bits have three each, the third uses four in parallel. This compensates for the variation in ON resistance from one hex buffer to the next; the error in the first two bits should track while that in the third may jump. The 50 kohm resistors in the ladder require less than a 500 ohm drive resistance for 1% accuracy and less than 50 ohms for .1% absolute accuracy. The buffers are typically 200 ohms resistance when HI at 25ºC but may be as poor as 600 ohms. Therefore, there are two important considerations, absolute accuracy and monotonicity. Absolute accuracy is not as important as monotonic output since the actual response must be calibrated anyway (the analog channels having the major uncertainty). Although no problem was detected in any of the six flight units, it appears there could be a nonlinearity if the worse combination of buffers between the three were applied, and for critical applications it will be useful to check their characteristics prior to circuit fabrication, using the lowest value of r as U1, next as U4 and highest for U7. If allowable, a future design might use quad switches such as the CD-4066, biased at 12 V and switching the 8 V reference to obtain consistently lower impedances. Three of those packages would have 12 switches allowing two parallel for the first two bits for a typical 50 ohm ON resistance at the two most critical points. An even better switch is the Harris Semiconductor HI-5051 which is 50 ohms maximum over the full military temperature range and 25 ohms typical at room temperature. These are logically compatible but only contain two DPDT switches per package so that 5 are required for the full complement. They could replace U1 and U4 only with no increase in package count.

 

Figure 5, "Detailed Circuit Timing," shows the A/D converter sequence. Note again that the multiplexing signals are generated by the "A" and "B" master counter and the output data runs one clock time behind the bit under conversion. The "Output Time" level is synchronized with the data and instructs the experiment Data logic to read the output. However, the "A" and "B" levels change at the least significant bit which complicates the data storage. This could be improved on future units by adding two binaries to provide a one clock time delay in the "A," "B" readout.

 

Multiplexing. Multiplexing is shown on the schematic for the 1520 board. One dual four channel multiplexer (U1) is used with its switches paralleled as the LEMPA mode current monitor multiplexer. The third and fourth switched points (pins 5/15 and 1/12) provide calibration inputs. Two 1 of 8 multiplexers are used for LEPT mode multiplexing (U2 and U3) with the second four inputs used to select the normal data for either D1 and D5 mode and the first four input points selecting the calibrate sequence. This is efficient in circuitry since the outputs of all three multiplexers are always summed. Thus two of the U1, U2, U3 lines are clamped to ground under any operating mode holding their respective multiplexers at the "0" input points while the third is high allowing its multiplexer to be scanned as the "A" and "B" lines count. The "C" input selects the normal or calibrate condition. U2 and U3 are grounded on their "O" input point producing no offset while U1 is providing LEMPA data. U1 has about 16 millivolts at its "O" input point for use as a 0.2% reference level during LEMPA calibration. LEPT mode uses only 8 of the 10 available bits with a resolution of 32 millivolts so that U1 introduces a constant 1/2 LSB offset in the data which is considered trivial. This error may readily be corrected if required; for example, the R10 calibration resistor might be replaced by two in series of 50 kohms each with a diode at the center tied to the U1 logic control line, thus reducing the offset during LEPT mode to less than 2 mV. Or the R10 resistor could be driven from the U1 line directly since an accuracy of about 25% is sufficient at this low calibration level.

 

Multiplexer selection is determined by the state of the LEPT/LEMPA (L/L) level, and the D1/D5 select level. The L/L input sets the U1 control LO when L/L is HI clamping the U1 multiplexer (board 1524) to the "0" condition. A HI D1/D5 input clamps the U3 control LO selecting the D1 input signal. The U2 control is LO if D1/D5 is LO selecting the D5 input signal. The calibrate input drives all three multiplexers selecting the 0 through 3 inputs of U3 and U2 and the 0 and 1 input of U1 if HI (calibration mode), and the 4 through 7 inputs of U2 and U3 and 2 and 3 of U1 when LO for normal mode. The four steps during a readout are generated by the "A" and "B" binaries which control the U2 and U3 multiplexers at their A and B inputs. Only the "A" level is used for the U1 multiplexer generating two repetitive cycles of the data.

 

Multiplexer power is switched from a hex inverter (pin 12 of U4, ID-1554)to obtain a low impedance ground during standby conditions for enhanced radiation resistance. In addition, the Vss line is switched to -1.2 V when ON (at the recommendation of JPL to further harden the circuit). All inputs are resistor isolated since they will be continuously driven from the Peak Detectors (if in LEPT mode) and Current Monitors. The small capacitors in the signal lines are used to minimize noise coupling while maintaining sufficient settling speed.

 

Figure 4 shows the analog errors in the A/D conversion and Multiplexing. The multiplexers are just low enough in ON resistance to accomplish the desired accuracy of 1% in LEPT and 0.1% in LEMPA mode which is a major contributor to the difference in accuracy. The TRW 1/4% resistors are small components with excellent stability but will require slight trimming with additional series resistance if true 0.1% absolute accuracy is ever desired. Refer to the Calibration Table for the measured environmental characteristics of the six units fabricated.

 

The Calibration Table is interesting. A comparison of all the data and the Figure 4 Error Block Diagram suggests the test system was introducing an offset error of about -10 mV. This probably occurred in the ground return lead between the boards under test and the test control boxes. The test offset error is needed to explain the inconsistency between the calibration readouts, measured most significant bit values, and measured total reading offset. The Error Diagram suggests a maximum gain error for the MSB of about 0.7% with the LEMPA commutator. The MSB is expected to have a value of between 3.972 and 4.028 volts so that the measured values are reasonable. The comparator is tailored to establish a LEMPA 0.2% calibration of 0002 counts which corresponds to an input of 15.7 mV ±4. This establishes a room temperature offset voltage of less than 4 mV and probably less than 2 mV overall since the tailoring is adjusted for the center of the correct readout.   Thus the measured system offset is inconsistent.  Future tests should be accomplished with both voltmeter leads routed through independent wiring to the circuit board inputs rather than at the Test output.

 

The multiplexing circuit introduces uncertainty as illustrated in Figure 4, "PHA Basic Error Block diagram." The ON resistance of U2 and U3 is 200 ohms or less which is about 0.7% of the total input drive resistance to the U4 inverting amplifier during LEPT Mode. The input isolation resistors are 10 k ohm, 1% contributing an additional 100 ohm uncertainty. These errors are not significant with respect to the uncertainty of the prior analog signal processing and should shift only a fraction of the absolute error with temperature. Checks of the three units fabricated to date show typical tracking errors across the multiplex of 0.2% with one channel showing close to a 1% error over the environment.

 

LEMPA operation is more critical since all 10 bits are used and the accuracy is enhanced by providing a greater input voltage (8 V instead of 2 V full scale) and lower multiplexer ON resistance. The major absolute error is contributed by the 1/4% MAR-3 resistors; however, this remains constant over the channels. Relative error between channels amounts to 100 ohm from the 10K 1% resistors and the multiplexer deviation. Measurements show consistently better than 0.1% channel to channel tracking over the environment in the LEMPA mode.

 

Note that the Error Diagram does not include the ladder driver error, which can be important, as previously discussed.

 

Continue

 

 

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VOYAGER 1 ELAPSED TIME

Days: Hours: Minutes: Seconds

*Since official launch
September 5, 1977, 12:56:00:00 UTC

VOYAGER 2 ELAPSED TIME

Days: Hours: Minutes: Seconds

*Since official launch
August 20, 1977, 14:29:00:00 UTC

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