VOYAGER

Voyager LECP Data Analysis Handbook

 

Calibrations and Channel Definitions

 

The Voyager (MJS) LECP Pulse Height Analyzer (PHA)

 

Circuit Detail (continued)

 

Peak Detector Circuitry (LEPT Monitors). The Peak Detector Circuitry and the associated logic is shown as the Schematic for the PHA 1570 board. The EME hybrid design is discussed in EME-75-186, "Hybrid Level Qualification of the EME-0267 PEAK DETECTOR" (archived at the Applied Physics Laboratory). The interface with the remaining PHA circuitry is illustrated in Figure 2, "Block Diagram, Pulse Height Analyzer."

 

Each of the five logarithmic analog inputs from the experiment LEPT section (D1 through D5) drives a peak detector hybrid and a discriminator hybrid as shown in the block diagram. The peak detector has a 100 nSec time constant in the positive direction and a dynamic range of at least 0 to 2.0 volts.  The schematic is given as EME-0267, "Schematic Diagram."  It includes a 5000 pfd NPO amplitude storage capacitor (C3) and a 2N4858 reset FET (Q5).  The "hold" function is accomplished by biasing the #3 pin to one diode drop above the +6 V power bus, thus keeping Q4 OFF and removing drive from the output transistor and diode.  The output will be driven up to the maximum value of the input level during normal operation with positive inputs, held at that value for one millisecond during a data conversion when requested and reset for about six microseconds after data conversion or two microseconds after the next zero crossing if no data is requested.  The delay and reset timing is generated on the 1570 board which also mounts the buffer amplifiers.

 

External 33Megohm bias resistors were added after test showed some of the hybrids would drift positive when cold.  This is inherent from the N channel input differential FET as the gate leakage charges the output capacitor.  A diode (CR1) is provided in the hybrid to generate a net negative current at the feedback node; however, the temperature coefficient of the diode is greater than that of the JFET's in some cases resulting in the positive drift.  The 22 Mohm resistors held at -.55 V bias cured the drift.   They create a time constant of about 10^-1 second or about a 1% discharge in the required 1 mSec maximum conversion interval. The JFETs were selected for a low gate leakage which is typically 20 picoamperes at 35ºC.  Note that the output capacitor is connected to two JFETs, one in the peak detector and another in the following Buffer Amplifier (EME-0268).  The 22 Mohm resistor is the largest value obtainable at the time of fabrication; a larger value of up to about 200 Megohm would introduce less error, a constant current drain of about 2 nA for zero output.  This would be especially effective if a temperature dependent bias voltage were used to compensate as the JFET leakage increased hot.  Maximum gate current at 25ºC is specified as 200 picoamperes.

 

The Peak Detector is tailored for minimum offset voltage error.  The least significant bit used in LECP operation is the 8th with a corresponding value of about 10 mV at the Peak Detector.  Full scale is defined as 2.0 volts which allows for operation from -50 to +50ºC and ±6.0 V + 10% on the power supplies.  If larger inputs are required, the positive power supply voltage should be raised accordingly in order to maintain the FETs in the pentode region and keep the offset balance error to less than 20 mV deviation.  The manufacturer specifies less than 1 mV balance change over the temperature environment which corresponds closely to the 2 mV change noted for both Peak Detector and Buffer in the flight units.  Note the thermal drift is minimized if the original trim is accurate and the room temperature offset at about 1 mV or less.

 

The following table of characteristics summarizes the peak detector hybrid:

 

	EME 0267 Characteristics
Input current:	-100 picoamperes max @ 25ºC
Offset Voltage:	Trimmable to less than 1 mV, 1 mV max shift with temp. 20 mV worse case shift at 2.0 V input, +50ºC and +5.5 volts power.
Output:	Zero to 2.00 V from 1 K ohm in series with 5000 picofarad
Reset:	To within 2 mV of ground within 3 uSeconds @ 25ºC, linear with absolute temperature.
Reset drive:	-6 V for OFF, +0.6 V for Reset.
Hold:	Amplifier unbalanced, will ignore up to +5 V input.
Hold drive:	Ground for normal operation, +0.6 V above +6 V bus for Hold.
Output drift:	Supply external pull down current of 2 nA or greater to assure no positive drift at cold temperatures.
Hold drift:	Will maintain 1% or 6 mV over 1 millisecond at output during hold if external load (Buffer Amplifier) is less than 2 nAmp.
Tracking speed:	Output time constant of less than 150 nanosecond.
Power required:	+6.0 V @ 1.6 mA ±0.2 -6.0 V @ 1.6 mA ±0.2
Special requirement:	Bracket "Reset" time with "Hold" time to prevent high power currents.

 

The EME-0262 discriminator hybrids are used to determine the negative going zero crossing after a minimum height pulse in order to generate a reset pulse after a 2 microsecond delay. These use RCA transconductance amplifiers which require up to 7 uA input current from the D lines. A limiting 510 ohm resistor is provided in series with the inputs for protection of the drive circuitry, especially during the time the PHA is in LEMPA mode and all Peak Detection circuitry is unpowered.  The discriminator input current can generate up to 3.5 mV additional offset error at the Peak Detectors and will contribute to the temperature shift.  The amount is not significant in this application but can be eliminated in future designs if warranted by using separate input lines for the Peak Detectors and Discriminators with individual limiting resistors.   Note the present 1560 boards are tailored for offset after fabrication and a discriminator with the maximum specified input current may generate a problem with offset shift vs. temperature.

 

The discriminators are adjusted individually for desired threshold point according to the relationship:

 

                          V_T ~= 1.3 x 10^-4 R_T

 

for V_T < 0.5V

 

Each unit is slightly different so that individual tailoring is required.  The values for the threshold levels are chosen to minimize detection of background noise (which would otherwise reset legitimate signals in other channels) while detecting the same lowest amplitude as the LEPT discriminators.  The levels remain fixed.  If future experiments use channels with variable minimum detection levels (as has been incorporated in a number of past devices) the Peak Detector Discriminator levels should track the main channel levels to prevent data error.  Otherwise an error can occur if the PHA retains a larger pulse than the main channel minimum detection level but lower than the PHA discriminator setting.

 

The 1570 board provides five buffer amplifiers (EME 0268) to follow the Peak Detectors with minimum current drain (same input specs as Peak Detectors). The peak timing logic is also on the 1570 circuit.  Figure 1, "Simplified Peak Detector Block Diagram," illustrates the logic operation. The five discriminators on the 1560 board drive the U7 NOR gates so that any one making a positive to negative transition (which occurs at zero cross following a detection) produces a positive transition at pin 14 of the U8 dual one shot (EME-0263B). This clocks the internal D flip-flop and initiates a 2 microsecond positive output at pin 13. The U7 pin 10 NOR gate produces a positive transition at pin 11 of U8 whenever all three inputs go to ground, thus generating the 6 microsecond reset signal. Thereby if a "Hold" positive level is received from the PHA "Run" flip-flop during the 2 microsecond delay interval, the Reset does not occur until the "Hold" level returns to ground about 1 millisecond later. The pin 10 output of U7 also drives the U6 pin 10 NAND to generate the Peak Detector Hold signal at board pin 29.  This signal is delayed using the RC output network and the U8 pin 10 discriminator of the 1560 board in order to bracket the following Reset pulse.   The discriminator threshold is set at 6.33 V with hysteresis dropping the negative threshold to 5.0 volts.  The RC delay maintains the Hold function during the time the Reset pulse initiates (note the output of U6 pin 10 may exhibit a short negative spike as the U7 pin 10 output goes high and the U8 pin 9 output has not yet transitioned low) and stretches the Hold past the completion of the Reset interval by about 0.5 microsecond.   The pulse timing is illustrated both by Figure 1 and in more detail at the board level on the 1570 schematic.

 

The buffer amplifiers (EME 0268) have two parallel outputs, each having an internal 1 kohm protect resistor to prevent loading by the OFF section of the redundant A/D converters.  They are also trimmed for minimum offset voltage after board fabrication and this is usually performed in conjunction with the 1560 board for best overall output offset.  Their specifications are essentially a low input current unity gain follower and are discussed in more detail as part of EME-75-193, "Electrical Test for EME-0268, Unity Gain Buffer" (archived at the Applied Physics Laboratory).

 

In summary, the Peak Detector circuitry uses five Peak Detectors and five Buffer Amplifiers to provide two outputs for each of the five D logarithmic channels, and one for each of the two redundant A/D converter multiplexers.  In addition, the two circuit boards (1560 and 1570) include logic and detection components to automatically reset the previous peak values two microseconds after a detected channel makes a negative going zero crossing unless a "Hold" level is received from either A/D converter at which time the detectors remain in the hold condition for the 1 millisecond data conversion interval.  The following table of characteristics, which summarizes the peak detector hybrid, is useful.

 

	PHA Peak Detector Circuit Specifications
Power Requirements:	+12.0 V @ 4 mA   8.0 @ 7 mA   6.0 @ 13 mA -6.0 @ 23 mA
Peak Dynamic Range and Accuracy:	2.00 V Full Scale, 20 mV max shift from -50 to +50ºC with 10% power deviation.  Error increases rapidly above full scale as JFETs depart from pentode region.  Use higher voltage on +6 V line for greater range.  Will detect positive peaks only.
Storage:	About 1% max droop in 1 millisecond.  Has 5000 picofarad output.
Reset:	Within 2 mV in 3 microseconds.
Reset Duration:	May be tailored, 6 microseconds in present system.
Delay Duration:	May be tailored, 2 microseconds in present system.
Channel Discriminators:	Set as desired; see Table on 1560 schematic.
Tailor Points:	Peak detector offset volts Buffer amplifier offset volts Delay time Reset duration
Off Characteristics:	All inputs and outputs resistor protected.

 

The following improvements might be useful in future designs of the Peak Detector circuitry:

 

1. Speedup of the EME 0267 hybrid by eliminating the internal C2 stabilizing capacitor and series R4 output resistor. This should be thoroughly evaluated to determine if significant overshoot can occur, but may be a very cost effective improvement since no new substrates would be required.
2. Use independent input drive of the Peak Detector and Discriminator hybrids to eliminate offset errors from the Discriminator input current and allow larger protective resistors.
3. Use a higher positive voltage on the Peak Detectors to increase the allowable dynamic range.
4. Design a better pull-down bias network for the Peak Detectors to increase the storage time and eliminate the internal CR-1 pull down bias diode.

 

The above changes may allow overall operational accuracy of a couple of millivolts over the full environment. A very high speed detector (less than 1 microsecond total pulse half-width as previously discussed with S1P group) will probably require two peak detectors in series, one to quickly set the peak voltage and a second to provide the required long storage.  The cascade allows a small storage capacitor in the first detector to quickly assume the desired peak and a larger capacitor in the second detector to charge slowly (over perhaps one microsecond) but maintain a small error with a realistic load (following buffer amplifier).

 

One additional system change is possible. At present the reset after a data conversion occurs at the end of the A/D conversion cycle, resulting in an additional 10 uSec dead time (out of the 1000 microseconds conversion interval).  Reset could occur one clock interval (20 uSec) earlier so that the system is immediately ready for another pulse; however, the improvement in dead time is rather small and requires an additional gate in the A/D control logic to cause Reset at the time the "C" binary switches high.

 

A primary reason for the hybrid amplifiers in the Peak Detector circuitry is the radiation sensitivity of all monolithic linear amplifiers and comparators evaluated and the severe environment of Jupiter encounter.  Other applications with more benign conditions may favor the adoption of monolithics at a significant cost reduction.

 

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VOYAGER 1 ELAPSED TIME

Days: Hours: Minutes: Seconds

*Since official launch
September 5, 1977, 12:56:00:00 UTC

VOYAGER 2 ELAPSED TIME

Days: Hours: Minutes: Seconds

*Since official launch
August 20, 1977, 14:29:00:00 UTC

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