Voyager LECP Pages
Tailoring the Pulse Height Analyzer
The following points must be individually tailored after board fabrication:
Tailoring is accomplished on the board tester using extenders to allow board plug in to the connector mounts. Typically a set of A/D converter boards is tailored and tested as a unit although the boards should be interchangeable upon completion. The Peak Detector boards have a separate test chassis and are tailored as a set of two.
A/D Converter Tailor. The A/D converter contains four boards as follows. A complete PHA has two redundant sets of A/D boards which are identical in pairs except for the 1530 board. The 1530-1 includes the U4 EME-0265 FET power switch and associated components for controlling the Peak Detector circuitry power while the 1530-2 board does not have those components mounted.
|1520 Board||Fast comparator and MPX. Tailor U4 and Fast Comparator offsets.|
|1530 Board||Reference voltage and Power switching. Tailor Reference Voltage|
|1540 Board||A/D cycle logic and ladder drivers. No tailor points.|
|1550 Board||Experiment interface and standby logic. No tailor points.|
Peak Detector Tailor
|1560 Board||Peak Detectors and Discriminators. Tailor offsets and thresholds.|
|1570 Board||Buffer Amplifiers and peak logic. Tailor offsets and one-shots.|
In the following descriptions, the boards are connected to the test chassis and controlled by the PHA test set. Each has been inspected and every resistor verified with a low voltage digital ohmmeter prior to tailoring. Confirm power currents are normal and voltages correct. Refer to the Layout drawings to identify components and pins on the boards.
1520 BOARD TAILORING
Set the Test Set controls to LEMPA MODE, CAL, VERT MAN STEP. This kills the clock input and holds the PHA in the conversion cycle at channel 1, the 0.2% calibration input. Power currents should read the conversion values. Short pin 1/12 of U1 to ground to provide a zero input voltage for U4. Trim U4 for minimum offset voltage (less than 1 mV at pin 15; be sure to reference the DVM ground at the board) by adjusting R43 and connecting it to either pin 3 or 5 for positive or negative corrections respectively. Install the required resistor and jumper then retest to confirm the offset. Remove the short at pin 1 of U1 on completion of this test.
After trimming U4 the Fast Comparator offset is corrected. This circuit uses current trim into the Q1 PNP current mirror (so do all the hybrids). The current corrects for two primary errors, the offset voltage of the 2N5564 JFET pair (which is specified as less than 5 mV) and the base emitter offset voltage of Q1. The sensitivity is about 30 uAmperes trim current for 8 mV (one bit) shift at the comparator input and varies with the transconductance of the JFETs. R35 will cause a positive deviation (more input voltage at the detection point) while R36 generates a negative deviation. 100 kohms at either point should cause about a 26 mV shift. Note the reference point for the tailor resistors is AC coupled to the +12 V bus to minimize noise as previously discussed.
Fast Comparator trim is defined as setting the LEMPA channel 1 0.2% calibration readout at the center of the second bit (reads 0002). Set the Test Set for normal operation in LEMPA MODE, CALIBRATE. Observe the channel 1 readout during the tailor operation. Determine the current required to shift the readout to a reading of 0001 and also 0003. Define a current through R35 as negative (readout counts will drop) and through R36 as positive. Use 11.4 volts as the voltage across a total resistance of RT + 10 kohms. The desired trim current is then the median of the two values calculated. Install the calculated trim resistor and confirm its value by checking the additional current now required to shift the calibration to 0001 and 0003. An identical current of about 14 uA into each tailor node should shift the bit, and therefore a resistor of about 500 kohms (22 uA injected) should shift the count back and forth when connected across R35 and R36 respectively. The resistor value will vary with the transconductance of the JFETs. An initial error of less than 1 mV is desired corresponding to about 4 uAmp uncertainty.
1530 BOARD TAILORING
There are three adjustments in setting the Reference Voltage. Trim is provided for the CR-1 reference zener bias current, U1 offset voltage, and precision divider U2 voltage feedback. The completed board will have a reference output of 8.000 V ±5 mV.
The PHA Test Set is set to the LEPT mode and VERT MAN STEP to keep the A/D converter circuit under continuous power.
R4 will have been originally installed as 3.0 kohms. Measure the CR-1 reference voltage directly at the board with a DVM. Calculate the R4 range which will maintain a bias current of 500 uA ± 50 uA and have R4 changed if the 3.0 kohm value is outside the range.
Connect the DVM directly across the U1 pins 7 and 9. Adjust the R1 tailor resistor for an error of less than 1 mV.
Monitor the Reference Voltage using the board pins and short sections of the U2 Precision Divider until a value of 8.000 V ± 4 mV is obtained. Have the jumpers installed and confirm the trim. Note that it may be necessary to install the more significant jumpers prior to making the fine adjustment for best results. Read the reference voltage at the test control box and note the error introduced by the test wiring.
Figure 6, Internal Power Switches for LECP PHA System
PEAK DETECTORS 1560 BOARD TAILORING
This board may be monitored by using miniature test hooks cut for the smallest practical hook. The hooks will easily pick-up individual hybrid leads for monitor. Short each input at the board when adjusting the voltage offset errors and keep both DVM leads at the board pins. Set the control box to "Hold," allow the output of the peak detector to drift negative, then release the "Hold" and observe the zero reference output. Less than 1 mV error is required for each of the five peak detectors. Use the schematic and layout drawings to identify the required monitor points and tailor resistors. Allow the board at least one minute to warm up prior to attempting adjustment and confirm each offset and record after the desired resistor is installed. The original value may be determined using either a decade box or individual MEA resistors. The short leads of the discrete resistors appear to improve the reproduceability between the preliminary and final results.
The discriminator thresholds should be set dynamically using pulse waveforms identical to those expected since there is some shift in response at the speeds of interest. A barrel type pulse shaping network is available which is used with the DC output of the mercury relay pulse generators for pulse simulation. The test control box provides an oscilloscope monitor point and the desired amplitude is monitored on the CRT while trim resistors are connected.
1570 BOARD TAILORING
The buffer amplifiers tailor for less than 1 mV error. The test control box is set to "Hold" which disconnects the output circuitry of the Peak Detectors, and the input pins for the Buffers may then be shorted to board ground to provide the zero reference value. Connect the DVM between the Buffer output pin and board ground, then trim as required. Use the schematic and layout drawing to determine circuit points. Verify the trim after installation of the final resistors. Then check the combination of Peak Detector and Buffer Amplifiers for less than 2 mV total error output.
The U8 one-shots can be verified by driving one of the D inputs with the normal channel shaped pulse at a level greater than its respective discriminator threshold and observing the corresponding delay and reset timing. Two timing capacitors are provided for at each oneshot and the following criteria should be met:
U8 ONE-SHOT ADJUSTMENT
|Pin 13 output:||2.0 to 2.6 uSeconds, trim with C3 and C4|
|Pin 9 output:||6.0 to 8.0 uSeconds, trim with C6 and C5|
Use of the mercury pulser (60 Hz rep rate) provides plenty of reset time for the one-shots to recover prior to the next pulse. If a different stimulus is used, keep the repetition rate slower than 10 kHz.
The tailoring operation is also a good time to verify operation of the logic and its timing as illustrated on the schematic. Verify each of the waveforms illustrated to confirm all the components are correct and the threshold levels of the hold delay networks proper. The timing diagram also shows the approximate amplitudes of the various waveforms which are somehwat critical.
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Last modified 6/20/03, Tizby Hunt-Ward